HDMI Signal Communication Over An Optical Link

ABSTRACT

Systems and methods for HDMI signal communication over an optical communication link are described. One aspect includes receiving an HDMI control signal from an HDMI master device, and another HDMI control signal from an HDMI sink terminal via a communication resources. The method identifies half-duplex communication resource contention between the HDMI control signal and the other HDMI control signal, and transitions a communication direction of the half-duplex communication resources to give the HDMI control signal precedence over the other HDMI control signal. Subsequent to transitioning the communication direction, the method transfers the HDMI control signal to the HDMI sink terminal via the communication resources. Subsequent to transferring the HDMI control signal, the method again transitions the direction of the half-duplex communication resources, and transfers the other HDMI control signal to the HDMI master device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.17/729,771, filed Apr. 26, 2022, which is a continuation of U.S. patentapplication Ser. No. 17/219,591, filed Mar. 31, 2021, which claims thebenefit of Chinese Patent Application No. 202011276576.2, filed Nov. 16,2020. All of the foregoing are hereby incorporated herein by referencein their entirety.

BACKGROUND Technical Field

The present disclosure relates to systems and methods that communicateone or more HDMI signals over an optical communication link.

Background Art

With the continuous development of display technology, displayresolution continues to increase. The transmission rate of audio andvideo data ranges from 100 MHz to several gigahertz, to several tens ofgigahertz. Communication philosophies such as Fiber-to-the-Desk of adisplay transmission system is a key aspect in the development ofdisplay technology. In addition to the definition of high-speed signals,HDMI (high definition multimedia interface), DVI (Digital VisualInterface) and other display transmission protocols also stipulate fivelow-speed signals: a Serial Data Line (SDA) signal, a Serial Clock Line(SCL) signal, a Hot Plug Detection (HPD) signal, a Consumer ElectronicsControl (CEC) signal and an Audio Return Channel (ARC) signal. Thesesignals play an important role in display control (e.g., SDA and SCL),user manipulation (e.g., HPD), and audio feedback (ARC). Therefore, alow-cost, low-delay, high-reliability and high-compatibility opticalfiber transmission capability of these low-speed signals plays aparticularly important role in the realization of optical fiber HDMI andDVI.

However, SDA and SCL, which are half-duplex communication signals, areinherently not compatible with optical fiber communication because ofthis half-duplex nature, since a fiber optic channel supports onlyunidirectional communication. In addition, there is a bus arbitrationproblem in the single bus communication used by CEC, which alsoconflicts with the topology of point-to-point communication of opticalfiber communication. The (analog) ARC signal also has certainrequirements for the bandwidth of optical fiber transmission.

Contemporary solutions for HDMI protocol low-speed signal transmissionmay include techniques such as:

-   -   (1) A Direct Digital Control (DDC) signal at an HDMI signal        source is connected to a local EEPROM (Electrically Erasable        Programmable Read Only Memory), and the local EEPROM stores        Extended Display Identification Data (EDID) information of        general display equipment. A disadvantage of this scheme is that        the EDID information of the actual display device cannot be        read; hence the compatibility of the scheme is poor.    -   (2) EDID information at the display device is read after        powering on, and is then transmitted to the source by optical        fiber communication. The method can effectively copy the EDID of        the display device at the source, so that the EDID information        of the display device can be correctly read when the remote end        initiates Direct Digital Control (DDC) communication. However, a        shortcoming of this scheme is that it cannot support functions        such as High-bandwidth Digital Content Protection (HDCP), HDMI        Status and Control Data Channel (SCDC), clock extension, read        request (the function where the display device actively pulls        down the SDA signal to ask the source device to read its flag        bit), and so on.    -   3) In the store-and-forward mode, DDC information is received        first, and when the device side needs to respond, the SCL signal        is actively pulled down to cause clock extension at the remote        end, thus waiting for the slave device to respond. When the        slave device responds, it returns to the source device and        cancels the clock extension. This scheme can read EDID normally,        support HDCP and SCDC, and extend the clock. However, a        disadvantage of this scheme is that the response delay is long,        and it is necessary to read the response from the slave device        before feeding it back to the source device. The scheme is not        effective when the source device does not support clock        extension. Therefore, the compatibility of this scheme is poor.        Moreover, in contemporary systems, there is no effective        solution to the bus arbitration problem of CEC communication.

SUMMARY

Aspects of the invention are directed to systems and methods fortransmitting one or more HDMI low-speed communication signals over anoptical communication link. In one aspect, an HDMI source terminalimplements a method to transmit and receive one or more HDMI controlsignals. A decoding and forwarding unit within the HDMI source terminalmay receive an HDMI control signal from an HDMI master device via anelectrical link. The HDMI source terminal may receive another HDMIcontrol signal from an HDMI sink terminal via optical communicationresources. The HDMI source terminal can internally convert the otherHDMI control signal and forward the other HDMI control signal to thedecoding and forward unit via another electrical link. The decoding andforwarding unit may identify communication resource contention betweenthe HDMI control signal and the other HDMI control signal. The decodingand forwarding unit can transition a communication direction ofhalf-duplex communication resources to give the HDMI control signalprecedence over the other HDMI control signal.

Subsequent to transitioning the communication direction, the HDMI sourceterminal may transfer the HDMI control signal to the HDMI sink terminalvia the half-duplex communication resources. Subsequent to transferringthe HDMI control signal, the HDMI source terminal may again transitionthe direction of the half-duplex communication resources, and transferthe other HDMI control signal to the HDMI master device.

A method to transmit and receive one or more HDMI control signals mayalso include the HDMI sink terminal receiving an HDMI control signalfrom an HDMI slave device. A decoding and forwarding unit within theHDMI sink terminal can receive the HDMI control signal via an electricallink. The HDMI sink terminal may receive another HDMI control signalfrom an HDMI source terminal via optical communication resources. TheHDMI sink terminal can internally convert the other HDMI control signaland forward the other HDMI control signal to the decoding and forwardunit via another electrical link. The decoding and forwarding unit mayidentify communication resource contention between the HDMI controlsignal and the other HDMI control signal. The decoding and forwardingunit can transition a communication direction of half-duplexcommunication resources to give the other HDMI control signal precedenceover the HDMI control signal.

Subsequent to transitioning the communication direction, the HDMI sinkterminal may transfer the other HDMI control signal to the HDMI slavedevice. Subsequent to transferring the other HDMI control signal, theHDMI sink terminal may again transition the direction of the half-duplexcommunication resources, and transfer the HDMI control signal to theHDMI source terminal via the half-duplex communication resources.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the present disclosureare described with reference to the following figures, wherein likereference numerals refer to like parts throughout the various figuresunless otherwise specified.

FIG. 1 is a block diagram depicting an example circuit architecture ofan HDMI optical communication system.

FIG. 2 is a block diagram depicting an example circuit architecture ofan HDMI source optical interface.

FIG. 3 is a block diagram depicting an example circuit architecture ofan HDMI sink optical interface.

FIG. 4 is a block diagram depicting an example circuit architecture ofan HDMI source terminal.

FIG. 5 is a block diagram depicting an example circuit architecture ofan HDMI sink terminal.

FIG. 6 is a block diagram depicting an interface between an HDMI sourceterminal and a master I2C.

FIG. 7 is a block diagram depicting an interface between an HDMI sinkterminal and a slave I2C.

FIG. 8 is a block diagram depicting a CEC connection topology.

FIG. 9 is a schematic diagram depicting a CEC connection topology thatuses a wired AND connectivity.

FIG. 10 is a schematic diagram depicting a CEC connection topology thatuses a CEC analyzer.

FIG. 11 is a schematic diagram depicting an encoding scheme for HDMIsignals.

FIG. 12 is a block diagram depicting an example system architecture ofmultiple HDMI sources connected to a single HDMI display device.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanyingdrawings that form a part thereof, and in which is shown by way ofillustration specific exemplary embodiments in which the disclosure maybe practiced. These embodiments are described in sufficient detail toenable those skilled in the art to practice the concepts disclosedherein, and it is to be understood that modifications to the variousdisclosed embodiments may be made, and other embodiments may beutilized, without departing from the scope of the present disclosure.The following detailed description is, therefore, not to be taken in alimiting sense.

Reference throughout this specification to “one embodiment,” “anembodiment,” “one example,” or “an example” means that a particularfeature, structure, or characteristic described in connection with theembodiment or example is included in at least one embodiment of thepresent disclosure. Thus, appearances of the phrases “in oneembodiment,” “in an embodiment,” “one example,” or “an example” invarious places throughout this specification are not necessarily allreferring to the same embodiment or example. Furthermore, the particularfeatures, structures, databases, or characteristics may be combined inany suitable combinations and/or sub-combinations in one or moreembodiments or examples. In addition, it should be appreciated that thefigures provided herewith are for explanation purposes to personsordinarily skilled in the art and that the drawings are not necessarilydrawn to scale.

Embodiments in accordance with the present disclosure may be embodied asan apparatus, method, or computer program product. Accordingly, thepresent disclosure may take the form of an entirely hardware-comprisedembodiment, an entirely software-comprised embodiment (includingfirmware, resident software, micro-code, etc.), or an embodimentcombining software and hardware aspects that may all generally bereferred to herein as a “circuit,” “module,” or “system.” Furthermore,embodiments of the present disclosure may take the form of a computerprogram product embodied in any tangible medium of expression havingcomputer-usable program code embodied in the medium.

Any combination of one or more computer-usable or computer-readablemedia may be utilized. For example, a computer-readable medium mayinclude one or more of a portable computer diskette, a hard disk, arandom-access memory (RAM) device, a read-only memory (ROM) device, anerasable programmable read-only memory (EPROM or Flash memory) device, aportable compact disc read-only memory (CDROM), an optical storagedevice, a magnetic storage device, and any other storage medium nowknown or hereafter discovered. Computer program code for carrying outoperations of the present disclosure may be written in any combinationof one or more programming languages. Such code may be compiled fromsource code to computer-readable assembly language or machine codesuitable for the device or computer on which the code can be executed.

Embodiments may also be implemented in cloud computing environments. Inthis description and the following claims, “cloud computing” may bedefined as a model for enabling ubiquitous, convenient, on-demandnetwork access to a shared pool of configurable computing resources(e.g., networks, servers, storage, applications, and services) that canbe rapidly provisioned via virtualization and released with minimalmanagement effort or service provider interaction and then scaledaccordingly. A cloud model can be composed of various characteristics(e.g., on-demand self-service, broad network access, resource pooling,rapid elasticity, and measured service), service models (e.g., Softwareas a Service (“SaaS”), Platform as a Service (“PaaS”), andInfrastructure as a Service (“IaaS”)), and deployment models (e.g.,private cloud, community cloud, public cloud, and hybrid cloud).

The flow diagrams and block diagrams in the attached figures illustratethe architecture, functionality, and operation of possibleimplementations of systems, methods, and computer program productsaccording to various embodiments of the present disclosure. In thisregard, each block in the flow diagrams or block diagrams may representa module, segment, or portion of code, which includes one or moreexecutable instructions for implementing the specified logicalfunction(s). It is also noted that each block of the block diagramsand/or flow diagrams, and combinations of blocks in the block diagramsand/or flow diagrams, may be implemented by special purposehardware-based systems that perform the specified functions or acts, orcombinations of special purpose hardware and computer instructions.These computer program instructions may also be stored in acomputer-readable medium that can direct a computer or otherprogrammable data processing apparatus to function in a particularmanner, such that the instructions stored in the computer-readablemedium produce an article of manufacture including instruction meanswhich implement the function/act specified in the flow diagram and/orblock diagram block or blocks.

Aspects of the invention described herein are configured to provide anHDMI optical communication system for wire-speed forwarding of HDMIprotocol low-speed signals. In one aspect, the HDMI opticalcommunication system may include an HDMI source interface and an HDMIsink interface communicatively coupled (i.e., connected) via afull-duplex optical communication channel (e.g., including two simplexoptical fibers, one optical fiber transferring data in each direction).In an aspect, the HDMI source interface and HDMI sink interface may eachinclude an electro-optical, half-duplex functionality. Collectively, theHDMI source interface, the HDMI sink interface, and the opticalcommunication channel, or portions thereof, may be referred to as“communication resources.”

In an aspect, the HDMI source interface may be configured to analyze oneor more HDMI source interface signals in real time, compress thesignals, and transmit the compressed signals to the HDMI sink interface.The HDMI source interface may also be configured to receive reversecommunication signals from the HDMI sink interface, decompress thereverse communication signals in real time, and transmit thedecompressed signals to an HDMI source.

In an aspect, the HDMI sink interface may be configured to analyze thesignals received from the HDMI source interface in real time, decompressthe signals, and transmit the decompressed signals to an HDMI sink(e.g., a display device). The HDMI sink interface may also be configuredto compress one or more signals generated by the HDMI sink insubstantially real time and transmit the compressed signals to the HDMIsource interface.

In an aspect, the HDMI source interface and the HDMI sink interface mayinclude an HDMI source terminal and an HDMI sink terminal, respectively.Each of the HDMI source terminal and the HDMI sink terminal may beconfigured to switch an input/output (I/O) direction of one or moreassociated signals according to specific communication conditions, torealize low-latency bidirectional communication over an opticalcommunication channel.

FIG. 1 is a block diagram depicting an example circuit architecture ofan HDMI optical communication system 100. As depicted, HDMI opticalcommunication system 100 includes a master I2C 102, an HDMI sourceinterface 104, an HDMI sink interface 106, and a slave I2C 108. In anaspect, HDMI source interface 104 may be communicatively coupled withHDMI sink interface 106 via a full-duplex optical communication channelcomprising an optical fiber 110 and an optical fiber 112. Optical fiber110 is a unidirectional (simplex) optical communication channelconfigured to communicate data from HDMI source interface 104 to HDMIsink interface 106. Optical fiber 112 is a unidirectional (simplex)optical communication channel configured to communicate data from HDMIsink interface 106 to HDMI source interface 104. Collectively, opticalfiber 110 and optical fiber 112 comprise a full-duplex opticalcommunication channel.

In an aspect, each of HDMI source interface 104 and HDMI sink interface106 may internally include half-duplex electro-optical communicationfunctionality. Collectively, HDMI source interface 104, HDMI sinkinterface 106, optical fiber 110 and optical fiber 112, or portionsthereof, comprise communication resources. In an aspect, thecommunication resources may be configured to communicate signals in ahalf-duplex manner.

In an aspect, master I2C 102 may be configured to transmit or receiveone or more signals associated with an HDMI protocol, to and from HDMIsource interface 104, respectively. In one aspect, these signals may below-speed HDMI signals. Master I2C 102 may transmit one or morelow-speed HDMI signals to HDMI source interface 104. In an aspect, theselow-speed HDMI signals may be electrical signals. HDMI source interface104 may convert these low-speed HDMI signals into optical low-speed HDMIsignals, and transmit the optical low-speed HDMI signals over opticalfiber 110 to HDMI sink interface 106. HDMI sink interface 106 mayconvert the received optical low-speed HDMI signals into electricallow-speed HDMI signals, and transmit these electrical low-speed HDMIsignals to slave I2C 108.

In an aspect, slave I2C 108 may be configured to transmit or receive oneor more signals associated with an HDMI protocol, to and from HDMI sinkinterface 106, respectively. In one aspect, these signals may below-speed HDMI signals. Slave I2C 108 may transmit one or more low-speedHDMI signals to HDMI sink interface 106. In an aspect, these low-speedHDMI signals may be electrical signals. HDMI sink interface 106 mayconvert these low-speed HDMI signals into optical low-speed HDMIsignals, and transmit these low-speed HDMI signals over optical fiber112 to HDMI source interface 104. HDMI source interface 104 may convertthe received optical low-speed HDMI signals into electrical low-speedHDMI signals, and transmit these electrical low-speed HDMI signals tomaster I2C 102. In this way, HDMI optical communication system 100 cantransmit one or more I2C signals associated with low-speed HDMIsignaling over a bidirectional optical channel.

In an aspect, master I2C 102 and HDMI source interface 104 communicateusing an inter-integrated circuit (I2C) communication protocol and HDMIsink interface 106 and slave I2C communicate using an inter-integratedcircuit (I2C) communication protocol. In one aspect, I2C communicationup to 400 Khz can be supported by HDMI optical communication system 100,which can fully meet the requirements of HDMI and DVI protocols (i.e.,low-speed signals associated with these protocols) at an I2Ccommunication rate. In addition, different timing implementations of I2Ccommunication may be used to perform different communication functionsassociated with low-speed HDMI or DVI signaling. For example, a clockextension of slave I2C 108 can be correctly reflected to master I2C 102using the I2C communication protocol.

In an aspect, HDMI optical communication system 100 may be implementedas a connecting cable that connects an HDMI source (e.g., a computer ora DVD player) with an HDMI sink (e.g., a computer display ortelevision). In such an implementation, I2C master 102, and HDMI sourceinterface 104 may be integrated into a first HDMI connector, and HDMIsink interface 106, and I2C slave 108 may be integrated into a secondHDMI connector. The first HDMI connector and the second HDMI connectormay be optically coupled using an optical communication channelcomprised of one or more optical fibers.

FIG. 2 is a block diagram depicting an example circuit architecture ofan HDMI source optical interface 200. As depicted, HDMI source opticalinterface 200 includes an HDMI source interface 202, an optical fiber220, an optical fiber 222, an optical fiber 232, an optical fiber 242,an optical fiber 252, and an optical fiber 262. HDMI source interface202 may further include an HDMI source terminal 204, a laser drivercircuit 228, a laser driver circuit 238, a laser driver circuit 248, anda photodetector PD 218. HDMI source interface 202 may also include oneor more vertical-cavity surface-emitting lasers (VCSELs), such as aVCSEL 216, a VCSEL 230, a VCSEL 240, a VCSEL 250, and a VCSEL 260.

In an aspect, each of laser driver circuit 228 through 258 is configuredto receive a pair of differential transition-minimized differentialsignaling (TMDS) signals associated with an HDMI signal, from an HDMIsignal source. For example, laser driver circuit 228 may receive aTMDS0+224 and a TMDS0−226 pair of signals; laser driver circuit 238 mayreceive a TMDS1+234 and a TMDS1−236 pair of signals; laser drivercircuit 248 may receive a TMDS2+244 and a TMDS2−246 pair of signals; andlaser driver circuit 258 may receive a TMDS3+254 and a TMDS3−256 pair ofsignals.

In an aspect, each of laser driver circuit 228 through 288 may beconfigured to transmit each pair of TMDS signals over an optical fiber,via a VCSEL. Each VCSEL receives electrical signals corresponding to aTMDS signal pair from an associated laser driver circuit, converts theelectrical signals to an optical signal, and transmits the opticalsignal over an optical fiber to an HDMI source interface. For example,laser driver circuit 228 may be configured to transmit TMDS0+224 andTMDS0−226 to VCSEL 230. VCSEL 230 converts TMDS0+224 and TMDS0−226 to anoptical signal and transmits the optical signal over optical fiber 232.Laser driver circuit 238 may be configured to transmit TMDS1+234 andTMDS1−236 to VCSEL 240. VCSEL 240 converts TMDS1+234 and TMDS1−236 to anoptical signal and transmits the optical signal over optical fiber 242.Laser driver circuit 248 may be configured to transmit TMDS2+244 andTMDS2−246 to VCSEL 250. VCSEL 250 converts TMDS2+244 and TMDS2−246 to anoptical signal and transmits the optical signal over optical fiber 252.Laser driver circuit 258 may be configured to transmit TMDS3+254 andTMDS3−256 to VCSEL 260. VCSEL 260 converts TMDS3+254 and TMDS3−256 to anoptical signal and transmits the optical signal over optical fiber 262.

In an aspect, HDMI source terminal 204 is configured to process,transmit, and receive one or more status and control signals associatedwith an HDMI communication protocol. Examples of HDMI status and controlsignals include SDA 206, SCL 208, CEC 210, ARC 212, and HPD 214. In anaspect, HDMI source interface 202 may implement one or more functionsthat are similar to HDMI source interface 104. For example, the HDMIstatus and control signals SDA 206 through CEC 210 may be received byHDMI source terminal 204 from master I2C 102. HDMI source interface 102may also be configured to transmit TMDS signals; this functionality isnot depicted in FIG. 1 .

In an aspect, HDMI source terminal 204 is configured to transmit SDA206, SCL 208, and CEC 210 to an HDMI sink interface, and receive ARC 212and HDP 214 from the HDMI sink interface. To further transmit (i.e.,forward) SDA 206, SCL 208, and CEC 210, HDMI source terminal 204 mayreceive these signals as electrical signals. HDMI source terminal 204may perform processing (e.g., time-division multiplexing and/or otherprocessing functions) on these signals, and transmit the processedsignals to VCSEL 216. VCSEL 216 converts these signals into opticalsignals and transmits the optically-converted signals to the HDMI sinkinterface via optical fiber 220.

In an aspect, photodetector PD 218 may be configured to receive SDA 206,SCL 208, CEC 210, ARC 212 and HPD 214 as time-division multiplexedoptical signals via optical fiber 222. PD 218 converts these opticalsignals into electrical signals and transmits these electrical signalsto HDMI source terminal 204. HDMI source terminal 204 may process thesereceived electrical signals (e.g., perform time-division demultiplexingon the signals), and transmit these signals to master I2C 102.

In an aspect, transmission and reception of SDA 206, SCL 208, CEC 210,ARC 212 and HPD 214 by HDMI source terminal 204 may be performed asseparate operations, in a half-duplex manner.

FIG. 3 is a block diagram depicting an example circuit architecture ofan HDMI sink optical interface 300. As depicted, HDMI sink opticalinterface 300 includes an HDMI sink interface 302, optical fiber 220,optical fiber 222, optical fiber 232, optical fiber 242, optical fiber252, and optical fiber 262. HDMI sink interface 302 may further includea PD 304, a VCSEL 306, a PD 320, a PD 328, a PD 336, a PD 334, and anHDMI sink terminal 308. HDMI sink interface 302 may also include one ormore transimpedance amplifiers (TIAs) such as a TIA 322, a TIA 330, aTIA 338, and a TIA 346.

In an aspect, PD 320 is configured to receive an optical signaltransmitted by VCSEL 230 over optical fiber 232; PD 328 is configured toreceive an optical signal transmitted by VCSEL 240 over optical fiber242; PD 336 is configured to receive an optical signal transmitted byVCSEL 250 over optical fiber 252; and PD 344 is configured to receive anoptical signal transmitted by VCSEL 260 over optical fiber 262.Essentially, PD 320 receives an optical equivalent of TMDS0+224 andTMDS0−226; PD 328 receives an optical equivalent of TMDS1+234 andTMDS1−236; PD 336 receives an optical equivalent of TMDS2+244 andTMDS2−246; and PD 344 receives an optical equivalent of TMDS3+254 andTMDS3−256;

In an aspect, each of PD 320 through 344 converts the respective opticalsignal into an electrical counterpart, and transmits the associatedelectrical signal to a transimpedance amplifier (TIA). Eachtransimpedance amplifier amplifies the electrical signal and generates aTMDS signal pair corresponding to a TMDS signal pair received andtransmitted by HDMI source interface 202. For example, PD 320 transmitsan electrical signal to TIA 322. TIA 322 amplifies the electrical signaland outputs a TMDS0+324 and a TMDS0−326 differential signal pair. TheTMDS 0+324 and TMDS 0−326 signals are received versions of thetransmitted TMDS signal pair TMDS0+224 and TMDS0−226, respectively.Also:

-   -   PD 328 transmits an electrical signal to TIA 330. TIA 330        amplifies the electrical signal and outputs a TMDS1+332 and a        TMDS1−334 differential signal pair. The TMDS1+332 and TMDS1−334        signals are received versions of the transmitted TMDS signal        pair TMDS1+234 and TMDS1−236, respectively.    -   PD 336 transmits an electrical signal to TIA 338. TIA 338        amplifies the electrical signal and outputs a TMDS2+340 and a        TMDS2−342 differential signal pair. The TMDS2+340 and TMDS2−342        signals are received versions of the transmitted TMDS signal        pair TMDS2+244 and TMDS2−246, respectively.    -   PD 344 transmits an electrical signal to TIA 346. TIA 346        amplifies the electrical signal and outputs a TMDS3+348 and a        TMDS3−350 differential signal pair. The TMDS3+348 and TMDS3−350        signals are received versions of the transmitted TMDS signal        pair TMDS3+254 and TMDS3−256, respectively.

The TMDS signals—TMDS0+324 through TMDS3−350 are transmitted to an HDMIsink.

In an aspect, time division-multiplexed signals SDA 206, SCL 208, andCEC 210 are received as optical signals by PD 304 via optical fiber 220.PD 304 may convert the optical signals to electrical signals andtransmit these electrical signals to HDMI sink terminal 308. HDMI sinkterminal 308 may process the received signals. This processing mayinclude time-division demultiplexing, among other operations. HDMI sinkterminal 308 outputs the processed signals as separate signals, e.g., anSDA 310, an SCL 312, and a CEC 314 that are received versions of SDA206, SCL 208, and CEC 210, respectively. Signals SDA 310, SCL 312 andCEC 314 may be transmitted by HDMI sink terminal 308 to an HDMI sink.

In an aspect, HDMI sink terminal 308 may receive SDA 310, SCL 312, CEC314, an ARC 316 and an HPD 318 signals from the HDMI sink. HDMI sourceterminal 204 may receive these signals as electrical signals. To furthertransmit (i.e., forward) the SDA 310, SCL 312, CEC 314, ARC 316 and HPD318 signals, HDMI sink terminal 308 may perform processing (e.g.,time-division multiplexing and/or other processing functions) on thesesignals, and transmit the processed signals to VCSEL 306. VCSEL 306converts these signals into optical signals and transmits theoptically-converted signals to the HDMI source interface via opticalfiber 222. Ultimately, these signals are received by HDMI sourceinterface 202 and output as SDA 206, SCL 208, CEC 210, ARC 212 and HDP214 signals, respectively.

In an aspect, transmission and reception of SDA 206, SCL 208, CEC 210,ARC 212 and HPD 214 by HDMI sink terminal 308 may be performed asseparate operations, in a half-duplex manner.

FIG. 4 is a block diagram depicting an example circuit architecture ofHDMI source terminal 204. As depicted, HDMI source terminal 204 includesan interface 402, a DDC decoding and forwarding unit 414, a CEC decodingand forwarding unit 416, a time division multiplex unit 418, signalcoding 420, a transmit (TX) circuit 422, a receiver (RX) circuit 424, asynchronization (sync) unit 426, channel decoding 430, a time divisiondemultiplex unit 432, a CEC arbitration 434, and an ARC driving unit436. Interface 402 may further include an SDA interface 404, an SCLinterface 406, a CEC interface 408, an HPD interface 410, and an ARCinterface 412. HDMI source terminal 204 may be configured to send andreceive signals via a bidirectional optical communication channel 428comprising optical fiber 220 and optical fiber 222.

In an aspect, HDMI source terminal 204 may be configured to send(transmit) and receive one or more HDMI control signals over an opticalcommunication channel (i.e., optical communication resources) thatincludes TX circuit 422, RX circuit 424, optical fiber 220 and opticalfiber 222. In an aspect, the HDMI control signals may include anycombination of an SDA signal, an SCL signal, a CEC signal, an HDPsignal, and an ARC signal.

In an aspect, one or more HDMI control signals may be transmitted byHDMI source terminal 204 using the optical communication resources. Thistransmission may be accomplished by time-division multiplexing the HDMIcontrol signals prior to transmission over the optical communicationchannel. The HDMI control signals may be transmitted to an HDMI sinkterminal such as HDMI sink terminal 308. The HDMI control signalstransmitted may be any combination of an SDA signal 438, an SCL signal442, and a CEC signal 446.

In an aspect, one or more HDMI control signals may be received by HDMIsource terminal 204 using the optical communication resources. TheseHDMI control signals may be received from an HDMI sink terminal such asHDMI sink terminal 308. The HDMI control signals received may be anycombination of an SDA signal 440, an SCL signal 444, a CEC signal 448,an HPD signal 450, and an ARC signal 454. In an aspect, these signalsare received as optical signals over optical fiber 222, in atime-division multiplexed format. RX circuit 424 may include one or morephotodetectors (e.g., PD 218) to convert the time-division multiplexedoptical signals into time-division multiplexed electrical signals. Thetime-division multiplexed electrical signals are received by sync unit426. Sync unit 426 is a synchronization unit that may be configured toperform bit synchronization and frame synchronization for the receivedsignals.

In an aspect, SDA interface 404 is configured to both transmit andreceive an SDA signal; SCL interface 406 is configured to transmit andreceive an SCL signal; and CEC interface 408 is configured to transmitand receive a CEC signal, with each transmission and receiving beingperformed in a half-duplex manner. SDA interface 404 and SCL interface406 may be connected to DDC decoding and forwarding unit 414. CECinterface 408 may be connected to CEC decoding and forwarding unit 416.DDC decoding and forwarding unit 414 may be configured to process DDCcommunication associated with HDMI source terminal 204. CEC decoding andforwarding unit 414 may be configured to process CEC communicationassociated with HDMI source terminal 204. In an aspect, CEC arbitration434 may be connected to CEC decoding and forwarding unit 416 and may beconfigured to perform CEC arbitration and prevent CEC signal conflicts.

Under certain circumstances, an HDMI control signal may be scheduled tobe transmitted to an HDMI sink terminal by HDMI source terminal 204, atthe same time that an HDMI control signal is received from the HDMI sinkterminal. This can lead to communication resource contention at HDMIsource terminal 204, for each of the SDA signal, the SCL signal, and theCEC signal (e.g., identified within unit 414 or unit 416). To address,and potentially preempt, any communication resource contention, thetransmitted and received SDA and SCL signals are processed by DDCdecoding and forwarding unit 414, while the transmitted and received CECsignals are processed by CEC decoding and forwarding unit 416 and CECarbitration 434.

In an aspect, when resolving any contention between SDA signal 438(being transmitted to an HDMI sink terminal) and SDA signal 440 (beingreceived from the HDMI sink terminal), DDC decoding and forwarding unit414 may run a protocol analysis state machine that prioritizes atransmission of SDA signal 438 over a reception of SDA signal 440. Inother words, for HDMI source terminal 204, SDA signal transmission istemporally prioritized over SDA signal reception. DDC decoding andforwarding unit 414 may transmit SDA signal 438 in substantially realtime at an interval of a local clock.

In an aspect, when resolving any contention between SCL signal 442(being transmitted to an HDMI sink terminal) and SCL signal 444 (beingreceived from the HDMI sink terminal), DDC decoding and forwarding unit414 may run a protocol analysis state machine that prioritizes atransmission of SCL signal 442 over a reception of SCL signal 444. Inother words, for HDMI source terminal 204, SCL signal transmission istemporally prioritized over SCL signal reception. DDC decoding andforwarding unit 414 may transmit SDA signal 442 in substantially realtime at an interval of a local clock.

In an aspect, when resolving any contention between CEC signal 446(being transmitted to an HDMI sink terminal and CEC signal 448 (beingreceived from the HDMI sink terminal), CEC decoding and forwarding unit416 may run a protocol analysis state machine that prioritizes atransmission of CEC signal 446 over a reception of CEC signal 448. Inother words, for HDMI source terminal 204, CEC signal transmission istemporally prioritized over CEC signal reception. CEC decoding andforwarding unit 416 may transmit CEC signal 446 in substantially realtime at an interval of a local clock.

In an aspect, time division multiplex unit 418 receives SDA and SCLsignals to be transmitted from DDC decoding and forwarding unit 414, anda CEC signal to be transmitted from CEC decoding and forwarding unit416. Time division multiplex unit 418 may be configured to cyclicallycollect and combine an SDA signal and an SCL signal to be transmittedfrom DDC decoding and forwarding unit 414, and a CEC signal to betransmitted from CEC decoding and forwarding unit 416. These signals arecombined into a single-channel signal using time-division multiplexing.In an aspect, the SDA, SCL, and CEC signals to be transmitted may becombined in any arbitrary temporal arrangement.

The time-division multiplexed signals generated by time divisionmultiplex unit 418 may be output to signal coding 420. Signal coding 420may be configured to perform Manchester encoding on the time-divisionmultiplexed signals. This enables synchronization between HDMI sourceterminal 204 and HDMI sink terminal 308. An output from signal coding420 is transmitted to TX circuit 422. TX circuit 422 is a transmission(transmit) circuit that is configured to convert one or more electricalsignals (containing the time-division multiplexed SDA, SCL and CECsignals) into optical signals for transmission over optical fiber 220.To achieve this functionality, TX circuit 422 may include one or moreVCSELs (e.g., VCSEL 216).

In an aspect, once the SDA, SCL and CEC signals (e.g., SDA signal 438,SCL signal 442, and CEC signal 446) have been transmitted, the receivedSDA and SCL signals (e.g., SDA signal 440, SCL signal 444) may betransmitted from DDC decoding and forwarding unit 414 to SDA interface404 and SCL interface 406, respectively. Also, the received CEC signal(e.g., CEC signal 448) received from the HDMI sink terminal may betransmitted from CEC decoding and forwarding unit 416, to CEC interface408. These SDA, SCL, and CEC signals are respectively transmitted fromSDA interface 404, SCL interface 406, and CEC interface 408, to masterI2C 102. In this way, half-duplex communication of the HDMI SDA, SCL andCEC signals using one or more optical resources is accomplished.

In one aspect, one or more HDMI signals may be received by HDMI sourceterminal 204 from an HDMI sink terminal via optical fiber 222. Thereceived signals may include SDA signal 440, SCL signal 444, CEC signal448, an HPD signal 450, and an ARC signal 452. These signals may bereceived in a time-division multiplexed format, as an optical signal. RXcircuit 424 may convert this optical signal into an electrical signalusing one or more photodetectors (e.g., PD 218). The electrical signalmay be received by channel decoding 430 that is configured to convertany received signals that are Manchester-encoded intonon-Manchester-encoded signals.

In an aspect, an output of channel decoding 430 may be received by timedivision demultiplex unit 432 that is configured to time-divisiondemultiplex the received signals, into:

-   -   SDA signal 440 that is transmitted to DDC decoding and        forwarding unit 414;    -   SCL signal 444 that is transmitted to DDC decoding and        forwarding unit 414;    -   CEC signal 448 that is transmitted to CEC decoding and        forwarding unit 416;    -   HPD signal 450 that is transmitted to HPD interface 410 for        further transmission to master I2C 102; and    -   ARC signal 452 that is transmitted to ARC driving unit 436 for        amplification and signal conditioning. ARC driving unit 436 may        generate an ARC signal 454 that is transmitted to ARC interface        412 for further transmission to master I2C 102. In an aspect,        ARC signal 454 is an analog signal.

In an aspect, among the HDMI SDA, SCL, HPD, CEC, and ARC signals, theARC signals have a requirement for the transmission bandwidth, so 50% ofthe time-division multiplexing time slice may be occupied in timedivision multiplexing by the ARC signal, while the remainingcommunication bandwidth may be equally divided among the four signalsCEC, HPD, SDA, and SCL.

In an aspect, HDMI source terminal 204 modulates one or more HDMIsignals (i.e., SDA, SCL and CEC) into a form suitable for transmissionover a physical (i.e., optical) channel. Generally, narrow-bandcommunication is adopted for wireless communication, and signals aremodulated onto high-frequency carriers for transmission, while PAM(Pulse Amplitude Modulation) can be adopted for copper wire or opticalfiber channels. By adopting the above communication protocol,communication delay is reduced to within 50 ns, and the compatibility ofa final display transmission scheme with different devices is realized.

FIG. 5 is a block diagram depicting an example circuit architecture ofHDMI sink terminal 308. As depicted HDMI sink terminal 308 includes achannel decoding 510, a sync unit 502, a receive (RX) circuit 504, atransmit (TX) circuit 508, a signal coding 508, a time divisiondemultiplex unit 512, a time division multiplex unit 518, a CECarbitration 516, a DDC decoding and forwarding unit 514, a CEC decodingand forwarding unit 520, an interface 534, an ARC driving unit 522, anSDA interface 524, an SCL interface 526, a CEC interface 528, an HPDinterface 530, an ARC interface 532, and an ARC driving circuit 522.HDMI sink terminal 308 may be configured to send and receive signals viaa bidirectional optical communication channel 428 comprising opticalfiber 220 and optical fiber 222.

In an aspect, HDMI source terminal 308 may be configured to send(transmit) and receive one or more HDMI control signals in a half-duplexmanner over an optical communication channel (i.e., opticalcommunication resources) that includes TX circuit 506, RX circuit 504,optical fiber 220 and optical fiber 222. In an aspect, the HDMI controlsignals may include any combination of an SDA signal, an SCL signal, aCEC signal, an HDP signal, and an ARC signal.

In an aspect, one or more HDMI control signals may be transmitted byHDMI sink terminal 308 using the optical communication resources. Thistransmission may be accomplished by time-division multiplexing the HDMIcontrol signals prior to transmission over the optical communicationchannel. The HDMI control signals may be transmitted to an HDMI sourceterminal such as HDMI source terminal 204. The HDMI control signalstransmitted may be any combination of SDA signal 440, SCL signal 444,CEC signal 448, HPD signal 450, and an ARC signal 452.

In an aspect, one or more HDMI control signals may be received by HDMIsink terminal 308 using the optical communication resources. These HDMIcontrol signals may be received from an HDMI source terminal such asHDMI source terminal 204. The HDMI control signals received may be anycombination of SDA signal 438, SCL signal 442, and CEC signal 446. In anaspect, these signals are received as optical signals over optical fiber220, in a time-division multiplexed format. RX circuit 504 may includeone or more photodetectors (e.g., PD 304) to convert the time-divisionmultiplexed optical signals into time-division multiplexed electricalsignals. The time-division multiplexed electrical signals are receivedby sync unit 502. Sync unit 502 is a synchronization unit that may beconfigured to perform bit synchronization and frame synchronization forthe received signals.

In an aspect, SDA interface 524 is configured to both transmit andreceive an SDA signal; SCL interface 526 is configured to transmit andreceive an SCL signal; and CEC interface 528 is configured to transmitand receive a CEC signal, with each transmission and receiving beingperformed in a half-duplex manner. SDA interface 524 and SCL interface526 may be connected to DDC decoding and forwarding unit 514. CECinterface 528 may be connected to CEC decoding and forwarding unit 520.DDC decoding and forwarding unit 414 may be configured to process DDCcommunication associated with HDMI sink terminal 308. CEC decoding andforwarding unit 520 may be configured to process CEC communicationassociated with HDMI sink terminal 308. In an aspect, CEC arbitration516 may be connected to CEC decoding and forwarding unit 520 and may beconfigured to perform CEC arbitration and prevent CEC signal conflicts.

In an aspect, sync unit 502 outputs received time-division multiplexedSCA, SCL, and CEC signals from an HDMI source terminal (e.g., HDMIsource terminal 204) to channel decoding 510. Channel decoding 510 maybe configured to convert any received signals that areManchester-encoded into non-Manchester-encoded signals. An output ofchannel decoding 510 is received by time division demultiplex unit 512.Time division demultiplex unit 512 may time-division demultiplex thesignal received from sync unit 502 to extract SDA signal 438, SCL signal442, and CEC signal 446. Of these signals, SDA signal 438 and SCL signal442 are transmitted to DDC decoding and forwarding unit 514, while CECsignal 446 is transmitted to CEC decoding and forwarding unit 520.

Under certain circumstances, an HDMI control signal may be scheduled tobe transmitted to an HDMI source terminal by HDMI sink terminal 308, atthe same time that an HDMI control signal is received from the HDMIsource terminal (e.g., HDMI source terminal 204). This can lead tocommunication resource contention at HDMI source terminal 308, for eachof the SDA signal, the SCL signal, and the CEC signal (e.g., identifiedwithin unit 514 or unit 520). To address, and potentially preempt, anycommunication resource contention, the transmitted and received SDA andSCL signals are processed by DDC decoding and forwarding unit 514, whilethe transmitted and received CEC signals are processed by CEC decodingand forwarding unit 520 and CEC arbitration 516.

In an aspect, when resolving any contention between SDA signal 438(being received from an HDMI source terminal) and SDA signal 440 (beingsent to the HDMI source terminal), DDC decoding and forwarding unit 514may run a protocol analysis state machine that prioritizes a receivingof SDA signal 438 over transmitting SDA signal 440. In other words, forHDMI sink terminal 308, SDA signal reception is temporally prioritizedover SDA signal transmission.

In an aspect, when resolving any contention between SCL signal 442(being received from an HDMI source terminal) and SCL signal 444 (beingsent to the HDMI source terminal, DDC decoding and forwarding unit 514may run a protocol analysis state machine that prioritizes a receptionof SCL signal 442 over a transmission of SCL signal 444. In other words,for HDMI source terminal 204, SCL signal reception is temporallyprioritized over SCL signal transmission.

In an aspect, when resolving any contention between CEC signal 446(being received from an HDMI source terminal) and CEC signal 448 (beingsent to the HDMI source terminal), CEC decoding and forwarding unit 520may run a protocol analysis state machine that prioritizes a receptionof CEC signal 446 over a transmission of CEC signal 448. In other words,for HDMI sink terminal 308, CEC signal transmission is temporallyprioritized over CEC signal reception.

In an aspect, the received SDA signal 438, SCL signal 442, and CECsignal 446 are transmitted to slave I2C 108 over interface 534, via SDAinterface 524, SCL interface 526, and CEC interface 528, respectively.

In an aspect, HDMI sink terminal may receive SDA signal 440, SCL signal444, CEC signal 448, HPD signal 450, and an ARC signal 536 from slaveI2C over interface 534, via SDA interface 524, SCL interface 526, CECinterface 528, HPD interface 530, and ARC interface 532, respectively.Of these signals, SDA signal 440 and SCL signal 444 are routed to DDCdecoding and forwarding unit 514, CEC signal 446 is routed to CECdecoding and forwarding unit 520, and ARC signal 536 is routed to ARCdriving unit 522. Of these signals, HDP signal 450 is directly routed totime division multiplex unit 518.

DDC decoding and forwarding unit 514 resolves any signal contentionbetween SDA signal 438 and SDA signal 440, and SCL signal 442 and SCLsignal 444. Once each signal contention is resolved to give temporalpriority to receiving SDA signal 438 and SCL signal 442, DDC decodingand forwarding unit 514 transmits SDA signal 440 and SCL signal 444 totime division multiplex unit 518.

CEC decoding and forwarding unit 520, in conjunction with CECarbitration 516, resolves any signal contention between CEC signal 446and CEC signal 448. Once this signal contention is resolved to givetemporal priority to receiving CEC signal 446, CEC decoding andforwarding unit 520 transmits CEC signal 448 to time division multiplexunit 518.

In an aspect, DDC decoding and forwarding unit 514 may transmit SDAsignal 440 and SCL signal 444 in substantially real time at an intervalof a local clock. CEC decoding and forwarding unit 529 may transmit CECsignal 448 in substantially real time at an interval of a local clock.

In an aspect, ARC signal 536 is an analog signal that is amplified andconditioned for transmission by ARC driving unit 522 to generate ARCsignal 452. ARC signal 452 is routed to time division multiplex unit518. In an aspect, ARC driving unit 522 may also be referred to as anARC amplifying unit.

In an aspect, time division multiplex unit 518 receives SDA signal 440and SCL signal 444 to be transmitted, from DDC decoding and forwardingunit 514. Time division multiplex unit 518 may also receive CEC signal448 to be transmitted from CEC decoding and forwarding unit 520. Timedivision multiplex unit 418 may be configured to cyclically collect andcombine SDA signal 440, SCL signal 444, CEC signal 448, HPD signal 450,and ARC signal 452. These signals are combined into a single-channelsignal using time-division multiplexing. In an aspect, the SDA, SCL,CEC, HPD, and ARC signals to be transmitted may be combined in anyarbitrary temporal arrangement.

The time-division multiplexed signals generated by time divisionmultiplex unit 518 may be output to signal coding 508. Signal coding 508may be configured to perform Manchester encoding on the time-divisionmultiplexed signals. This enables synchronization between HDMI sourceterminal 204 and HDMI sink terminal 308. An output from signal coding508 is transmitted to TX circuit 506. TX circuit 506 is a transmission(transmit) circuit that is configured to convert one or more electricalsignals (containing the time-division multiplexed SDA, SCL, CEC, HPD andARC signals) into optical signals for transmission over optical fiber222. To achieve this functionality, TX circuit 506 may include one ormore VCSELs (e.g., VCSEL 306). In this way, half-duplex communication ofthe HDMI SDA, SCL, CEC, HPD and ARC signals using one or more opticalresources is accomplished.

In an aspect, among the HDMI SDA, SCL, HPD, CEC, and ARC signals, theARC signals have a requirement for the transmission bandwidth, so 50% ofthe time-division multiplexing time slice may be occupied in timedivision multiplexing by the ARC signal, while the remainingcommunication bandwidth may be equally divided among the four signalsCEC, HPD, SDA, and SCL.

In an aspect, HDMI sink terminal 308 modulates one or more HDMI signals(i.e., SDA, SCL, CEC, HPD and ARC) into a form suitable for transmissionover a physical (i.e., optical) channel. Generally, narrow-bandcommunication is adopted for wireless communication, and signals aremodulated onto high-frequency carriers for transmission, while PAM(Pulse Amplitude Modulation) can be adopted for copper wire or opticalfiber channels. By adopting the above communication protocol,communication delay is reduced to within 50 ns, and the compatibility ofa final display transmission scheme with different devices is realized.

In an aspect, DDC decoding and forwarding unit 514 monitors the levelsof SDA and SCL signal lines (i.e., SDA interface 524 and SCL interface526) in real time. When clock extension and Read Request events aredetected at the display of the equipment (e.g., an HDMI sink connectedto slave I2C 108), the request is forwarded to the HDMI source terminal204, thus informing the source equipment (e.g., an HDMI source connectedto master I2C 102) to perform corresponding operations.

In an aspect, DDC decoding and forwarding unit 514 can analyze SDA andSCL signals sent by the HDMI source terminal 204, and feedbackacknowledgement (ACK) and read data from the display device to thesource equipment in time.

In an aspect, Manchester encoding may be used to encode all digitalsignals (i.e., SDA, SCL, CEC, and HDP signals) communicated between HDMIsource terminal 204 and HDMI sink terminal 308. This enablescommunication between HDMI source terminal 204 and HDMI sink terminal308 to be implemented without having to synchronize the clock signals ofHDMI source terminal 204 and HDMI sink terminal 308.

In an aspect, the communication protocols between HDMI source terminal204 and HDMI sink terminal 308 (also referred to as “wire-speedforwarding method”) are not limited to a specific I2C (inter-integratedcircuit) address, but can be applied to reading EDID signals,communication of HDCP and communication of SCDC. Compatibility can beachieved for all 128 addresses from 0x00 to 0x7F.

In an aspect, the functionalities of HDMI source terminal 204 and HDMIsink terminal 308 may be collectively described as “HDMI low-speedwire-speed forwarding.” Functionalities of HDMI source interface 104 andHDMI sink interface 106 that include high-speed HDMI signal transmissionmay be referred to as “HDMI high-speed signal forwarding.”

In one aspect, a circuit architecture for wire-speed forwarding of HDMIprotocol low-speed signals, as realized by a combination of HDMI sourceterminal 204 and HDMI sink terminal 308, supports EDID informationreading, HDCP, SCDC, clock extension and Read Request functions. A CECbus arbitration problem is solved, an audio return is realized and anARC port is driven, HPD signals are correctly controlled when cables arepulled out, and low cost, low delay, high reliability and highcompatibility of the HDMI scheme are ensured.

A combination of HDMI source terminal 204 and HDMI sink terminal 308solve the problem of half-duplex communication of active optical fiberlow-speed signals in optical transmission, by providing a circuit forwire-speed forwarding of HDMI protocol low-speed signals and adaptivelychange the (half-duplex) communication direction.

In one aspect, HDMI source terminal 204 analyzes HDMI source interfacesignals (i.e., SDA, SCL, and CEC signals) in substantially real time,compresses the signals using time-division multiplexing, and transmitsthe compressed signals to HDMI sink terminal 308. HDMI source terminal204 also receives reverse communication signals (i.e., SDA, SCL, CEC,HPD, and ARC signals) from the HDMI sink terminal 308, and decompresses(i.e., time-divison demultiplexes) the reverse communication signals insubstantially real time and transmits the decompressed signals to anHDMI source.

In one aspect, HDMI sink terminal 308 analyzes the signals (i.e., SDA,SCL, and CEC signals) received from the HDMI source terminal 204 insubstantially real time, decompresses the signals using time-divisiondemultiplexing, and transmits the decompressed signals to a displaydevice (i.e., an HDMI sink). HDMI sink terminal 308 also compresses(i.e., time-division multiplexes) the SDA, SCL, CEC, HPD and ARC signalsof the display device in substantially real time and transmits thecompressed signals to HDMI source terminal 204.

One or more analysis modules of HDMI source terminal 204 (i.e., DDCdecoding and forwarding unit 414, and CEC decoding and forwarding unit416) and one or more analysis modules of HDMI sink terminal 308 (i.e.,DDC decoding and forwarding unit 514, and CEC decoding and forwardingunit 520) switch IO (Input/Output) direction reasonably according tospecific communication conditions, and realize low-delay bidirectionalcommunication.

FIG. 6 is a block diagram depicting an interface 600 between HDMI sourceterminal 204 and master I2C 102. Interface 600 depicts internalcomponents of DDC decoding and forwarding unit 414. As depicted, HDMIsource 204 includes an IO direction control 602, a read request control604, a clock extension control 606, an IO direction control 608, a DDCslave state machine 610, a receiving unit 612, and a local oscillator614.

In an aspect, DDC slave state machine 610 is configured to resolve acontention between SDA signal 438 and SDA signal 440, and between SCLsignal 442 and SCL signal 444. In response to the contention resolution,IO direction control 602 and IO direction control 608 switch a directionof communication of SDA interface 404 and SCL interface 406respectively, to transition between receive and transmit modes. Forexample, IO direction control 602 may switch a direction ofcommunication of SDA interface 404 from an input (i.e., receiving SDAsignal 438 from master I2C 102) to an output (i.e., transmitting SDAsignal 440 to master I2C 102) once SDA signal 438 has been transmittedto HDMI sink terminal 308. This enables SDA signal 440 to be transmittedto master I2C 102 and then to an HDMI source associated with master I2C102.

In an aspect, receiving unit 612 is configured to receive unpacked SDAsignal 440 and unpacked SCL signal 444 (i.e., time-divisiondemultiplexed SDA signal 440 and time-division demultiplexed SCL signal444) from time division demultiplex unit 432. Local oscillator 614supplies a clock signal to DDC slave state machine 610 and othercomponents of HDMI source terminal 204.

In an aspect, DDC slave state machine 610 is configured to determinewhen to switch an IO direction for SDA interface 404 and/or SCLinterface 406, or when to pull down the IO for either or both of theseinterfaces. In an aspect, local oscillator 614 may be a 100 MHz-400 MHzreconfigurable on-chip ring oscillator to clock the DDC slave statemachine 610. DDC slave state machine 610 may be configured to performfiltering and reshaping operations on the DDC signals (i.e., the SDA andthe SCL signals). Read request control 604 and clock extension control606 may be configured to respectively support Read Request and clockstretching functions as defined in the HDMI protocol. In an aspect,functions of read request control 604 and clock extension control 606may be governed by DDC slave state machine 610.

FIG. 7 is a block diagram depicting an interface 700 between HDMI sinkterminal 308 and slave I2C 108. Interface 700 depicts internalcomponents of DDC decoding and forwarding unit 514. As depicted, HDMIsink 308 includes an IO direction control 702, a read request control704, a clock extension control 706, an IO direction control 708, a DDCslave state machine 710, a receiving unit 712, and a local oscillator714.

In an aspect, DDC slave state machine 710 is configured to resolve acontention between SDA signal 438 and SDA signal 440, and between SCLsignal 442 and SCL signal 444. In response to the contention resolution,IO direction control 702 and IO direction control 708 switch a directionof communication of SDA interface 524 and SCL interface 526respectively, to transition between receive and transmit modes. Forexample, IO direction control 602 may switch a direction ofcommunication of SDA interface 524 from an input (i.e., receiving SDAsignal 440 from slave I2C 108) to an output (i.e., transmitting SDAsignal 438 to slave I2C 108) prior to transmitting SDA signal 440 hasbeen transmitted to HDMI source terminal 204. This enables SDA signal438 to be transmitted to slave I2C 108 and then to an HDMI sinkassociated with slave I2C 108.

In an aspect, receiving unit 712 is configured to receive unpacked SDAsignal 438 and unpacked SCL signal 442 (i.e., time-divisiondemultiplexed SDA signal 438 and time-division demultiplexed SCL signal442) from time division demultiplex unit 512. Local oscillator 714supplies a clock signal to DDC slave state machine 710 and othercomponents of HDMI sink terminal 308.

In an aspect, DDC slave state machine 710 is configured to determinewhen to switch an IO direction for SDA interface 524 and/or SCLinterface 526, or when to pull down the IO for either or both of theseinterfaces. In an aspect, local oscillator 714 may be a 100M˜400 MHzreconfigurable on-chip ring oscillator to clock the DDC slave statemachine 710. DDC slave state machine 710 may be configured to performfiltering and reshaping operations on the DDC signals (i.e., the SDA andthe SCL signals). Read request control 704 and clock extension control706 may be configured to respectively support Read Request and clockstretching functions as defined in the HDMI protocol. In an aspect,functions of read request control 704 and clock extension control 706may be governed by DDC slave state machine 710.

In an aspect, DDC decoding and forwarding unit 414 and DDC decoding andforwarding unit 514 support single read-write or continuous read-writeoperation for any I2C device address, support pulling down theassociated SCL pin at the HDMI source to inform the HDMI source deviceof clock extension when HDMI source terminal 204 sends a clock extensionsignal. DDC decoding and forwarding unit 414 and DDC decoding andforwarding unit 514 may support pulling down the SDA pin of the sourceto inform the source device when the HDMI sink terminal 308 sends a ReadRequest signal, and requesting to initiate DDC communication to an A8address.

In an aspect, DDC decoding and forwarding unit 414 and DDC decoding andforwarding unit 514 each includes a DDC slave state machine (i.e., DDCslave state machines 610 and 710, respectively) operating insubstantially real-time, configured to forward communication signals insubstantially real-time according to the communication sent by a masterI2C. These DDC slave state machines may each update a communicationstate at the same time. Each state machine can analyze whether masterI2C 102 is waiting for an ACK signal (return signal) from slave I2C 108,or waiting for reading data in real time, thus switching IOcommunication direction and forwarding signals received from slave I2C108 to master I2C 102 in time to realize substantially real-time I2Ccommunication forwarding.

In an aspect, each of DDC decoding and forwarding unit 414 and DDCdecoding and forwarding unit 514 can analyze one or more instructions ofclock extension and Read Request according to the signals sent from I2C(i.e., master I2C 102 and slave I2C 108, respectively), and controlassociated SDA and SCL pins (interfaces) to forward these two requests.

In one aspect, power to HDMI source interface 104 may be provided by theHDMI source or an external input power supply. Power to HDMI sinkinterface 106 may be provided by the HDMI sink (i.e., the HDMI displaydevice) or an external input power supply. In one aspect, HDMI opticalcommunication system 100 can detect the plugging and unplugging state ofthe associated optical cable under the conditions of supporting HPDsignals, supplying power outside of HDMI sink terminal 308, or supplyingpower by the HDMI sink.

In one aspect, in the HDMI sink terminal 308, the ARC signals taken outfrom the Utility pin and the HPD pin are used to generate an ARC signalby subtracting signal a on an ARC pin (e.g., ARC interface 532) from asignal on HPD pin (e.g., HPD interface 530). In an aspect, this analogsignal subtraction may be performed using a differential amplifier. Theresultant ARC signal generated by the subtraction is amplified by theARC signal amplifying unit. After being transmitted to HDMI sourceterminal 204, ARC signal 452 is adjusted, by ARC driving unit 436, to alevel range conforming to the HDMI protocol specification for output,and a certain driving capability is provided. Specifically, ARC drivingunit 436 converts ARC signal 452 transmitted from the HDMI sink into ARCsignal 454 conforming to the HDMI level standard. ARC signal 454 may beused to drive a peripheral circuit.

In an aspect, the DDC slave state machine 610 functions as a DDC slave,in a sense that DDC slave state machine 610 when I2C master 102 iswriting or reading, or needs acknowledgment. This information istransformed to IO direction decisions by DDC slave state machine 610.For example, during writing, the IO direction is from the master I2C 102to slave I2C 108, while during reading and acknowledgment, the IOdirection is from I2C slave 108 to the I2C master 102. Similarly, DDCslave 710 state machine uses DDC signals transmitted from HDMI sourceterminal 204 to judge if I2C master 102 is writing or reading, or needsacknowledgment, and changes the IO direction accordingly.

For read request control, the read request is launched by HDMI sinkterminal 308, to inform HDMI source terminal 204 to read the statusinformation from slave I2C 108. In this case, read request control 704on the HDMI sink terminal 308 will check if I2C slave 108 is pullingdown the SDA signal for a long enough time to start a read request. Thisread request information is packed and transmitted through bidirectionaloptical communication channel 428 to the source HDMI terminal 308. Onreceiving the read request information, read request control 604 on HDMIsource terminal 204 will pull down the SDA signal for enough to informI2C master 102 accordingly.

FIG. 8 is a block diagram depicting a CEC connection topology 800. Asdepicted, CEC connection topology 800 depicts HDMI source terminal 204including components included in CEC decoding and forwarding unit 416.HDMI source terminal 204 may include an IO direction control 804, a CECanalyzer 806, a local CEC arbitrator 808, a CEC transmit and reshapeunit 810, and a local oscillator 812.

In an aspect, CEC analyzer 806 may be configured to receive CEC signal446 and CEC signal 448. Each of these signals may be received separatelyby CEC analyzer 806 as a CEC signal 802, and a CEC dual signal 814,respectively. Local CEC arbitrator 808 may be configured to analyze thereceived CEC signals and resolve contention between these signals.Responsive to local CEC arbitrator 808 resolving the contention, CECanalyzer 806 may be configured to switch an IO direction to prioritizetransmission of CEC signal 446. In an aspect, CEC transmit and reshapeunit only transmits the winner CEC signal from the contentionresolution. The CEC transaction direction of the associatedcommunication link is held until the end of the CEC transaction. Localoscillator 812 supplies a clock signal to the different components ofCEC decoding and forwarding unit 416.

A similar architecture may be used to implement CEC decoding andforwarding unit 520. In one aspect, CEC decoding and forwarding units416 and 520 each perform respective CEC signal decoding and determine anassociated UI direction. CEC arbitration units 434 and 516 respectivelymanage any associated arbitration between a local CEC bus transactionand a received CEC transaction unpacked from bidirectional opticalcommunication channel 428 to decide whether to forward the local CECtransaction or the received CEC transaction.

FIG. 9 is a schematic diagram depicting a CEC connection topology 900that uses a wired AND connectivity as implemented in the prior art. Inan aspect, the wired AND connectivity is used to realize a bidirectionalcommunication protocol associated with a communication bus such as a CECbus. As depicted, connection topology 900 includes a node 1 902, a node2 904, a node 3 906, a node 4 908, a node 5 910, a node 6 912, a node 7914, a node 8 916, and a node 9 918. Each node is connected to at leasttwo other nodes via a bidirectional wired AND communication link asdepicted in FIG. 9 .

In an aspect, each of node 1 902 through node 9 918 may represent a CECnode. Topology 900 may be subject to CEC bus deadlocks. For example,node 1 902 might send a CEC request to node 9 918. This CEC request sentby node 1 may sent back to node 1 after several CEC transactions (asindicated by the bidirectional dashed arrow paths in FIG. 9 ), and thisdelayed request will also be wire ANDed with the request being send outby node1 902. This occurrence of the CEC request being sent back to node1 902 is a result of full-time bidirectional wire AND paths beingimplemented in topology 900. The wire ANDing of the original requestfrom node 1 902 and the replica request received back at node 1 902 viaa route traced out by some combination of the bidirectional paths willcause CEC arbitration failure on node 1 902. This is one example of howa wired AND method may cause a deadlock on a CEC bus, which stops nodesfrom sending CEC requests.

FIG. 10 is a schematic diagram depicting a CEC connection topology 1000that uses a CEC analyzer, such as CEC analyzer 416. As depicted,connection topology 900 includes a node 1 1002, a node 2 1004, a node 31006, a node 4 1008, a node 5 1010, a node 6 1012, a node 7 1014, a node8 1016, and a node 9 1018. Each of node 1 1002 through node 9 1018 mayinclude a CEC analyzer such as CEC analyzer 416. Using CEC arbitrationlogic (i.e., using a CEC analyzer) enables connection topology 1000 toavoid CEC bus deadlocks as encountered on connection topology 900.

Returning to the example presented for topology 900, where node 1 902sends a CEC request to node 9 918, in topology 1000 CEC node (i.e., node2 904 through node 9 918) performs local CEC arbitration with anadjacent node using, for example CEC analyzer 416 or 420. The “CECtransmitter” will only transmit the winner CEC signal from thearbitration resolution. Furthermore, each communication link from eachnode to an adjacent node is held at a unidirectional transmission pathtill the CEC transaction is complete. In this case, all communicationlinks are held in their assigned unidirectional paths as depicted inFIG. 10 , till the CEC request from node 1 1002 to node 9 1018 iscomplete. As depicted in FIG. 10 , tracing any path along theunidirectional links starting at node 1 1002 ultimately leads to node 91018, without any ambiguity or any chance of the CEC request beingreturned to node 1 1002. This feature prevents any deadlocks on the CECbus. A communication direction of each unidirectional communication linkcan be arbitrarily switched by the associated CEC analyzer logic in theterminal nodes by appropriate CEC arbitration. Topology 1000 implementshalf-duplex CEC request communication over a mesh network whilevirtually eliminating any occurrence of CEC bus deadlocks.

Topology 1000 represents CEC arbitration communication that includes theprocess of CEC signal arbitration. HDMI source terminal 204, CECdecoding and forwarding unit analyzes the CEC signal of the HDMI sourceand forwards it to the display device (i.e., the HDMI sink) over theoptical communication resources, and CEC arbitration 434 determines thecommunication direction of CEC signals according to the signals of theHDMI source and the display devices.

In HDMI sink terminal 308, CEC decoding and forwarding unit 520 analyzesthe CEC signal of the display device (i.e., the HDMI sink) and forwardsit to the HDMI source over the optical communication resources, and theCEC arbitration unit determines the communication direction of CECaccording to the signals of the HDMI source and display devices.

In one aspect, the bus arbitration method in a CEC single buscommunication scheme is transplanted to point-to-point communicationsuch as optical transmission or wireless transmission as implemented intopology 1000, and the bus communication of CEC is mapped to routingcommunication in point-to-point communication by using the method oflocal arbitration and arbitration result routing.

Each node in topology 1000 represents a communication node of HDMI. Theoverall topology 1000 is the topology of an HDMI-based network, and acommunication mode associated with each of node 1002 through node 1018is point-to-point communication. In one aspect, each of node 1002through node 1018 has a local CEC arbitration unit similar to CECarbitration 434 or CEC arbitration 516, and each node conducts localarbitration. After the arbitration fails, the original communicationdirection will be switched, so the CEC communication that fails inarbitration will not be transmitted any more. For example, if node 81016 node in topology 1000 fails in arbitration, the communication sentby it will no longer be transmitted, and CEC communication sent by, forexample, node 4 1008 will be broadcast in the form of flooding in thewhole network.

FIG. 11 is a schematic diagram depicting an encoding scheme 1100 forHDMI signals. As depicted, encoding scheme 1100 includes an initial part1102 of a first data packet, a terminal part 1104 of the first datapacket, an initial part 1106 of a second data packet, and a terminalpart 1108 of the second data packet. In an aspect, each data packet mayinclude a sequence of signals: ARC, SDA, ARC, SCL, ARC, CEC, ARC, andHPD, with the sequence repeating. Inserting an ARC signal in every otherdata slot in the data packet ensures that the ARC signal is given therequired 50% bandwidth. The data structure of each packet is such thatthe analog ARC signal alternates with a piece of digital data. In oneaspect, digital data in each data packet may be encoded using Manchesterencoding. For example, logic 1 of a control signal may be encoded as111000. Encoding scheme may be used for all HDMI optical signalingsupported by HDMI optical communication system 100.

In one aspect, a start of a data packet is designated by an elongatedlast bit sequence from the data packet immediately before the datapacket, as indicated in FIG. 11 . In other words, the elongated bitsequence from the previous data packet acts as a header for the currentdata packet. For example, if the last bit sequence is 000111 of theprevious data packet, the header of the next packet is set to be 111111.In this case there will be 9 “1”s in a row, so the synchronization logiccan use a counter to detect the packet header. With this encoding, aclock difference of 16.6% between two link partners (e.g., HDMI sourceterminal 204 and HDMI sink terminal 308) can be tolerated. So, insteadof using off-chip reference clock as contemporary systems, HDMI opticalcommunication system 100 uses on chip ring oscillators to clock thewhole system.

In one aspect, the clocks on two sides of the link partner (i.e., theclocks on HDMI source terminal 204 and HDMI sink terminal 308) may becoarsely calibrated to approximately the same frequency. Thesynchronization method in this invention obviates the need of a clockand data recovery (CDR) system or of a precise reference clock.

In one aspect, the ring oscillator in each of HDMI source terminal 204and HDMI sink terminal 308 may be set to 400 MHz. This enables 40 MHzoversampling t be performed on ARC signals, which is sufficient for ARCsignal transmission.

FIG. 12 is a block diagram depicting an example system architecture 1200of multiple HDMI sources connected to a single HDMI display device. Asdepicted, system architecture 1200 includes a video source 1202, othercontrol devices 1206, audio equipment 1208, and a display device 1204.In aspect, display device 1204 is an HDMI display device. In an aspect,display device 1204 is individually communicatively coupled with each ofvideo source 1202, other control devices 1206, and audio equipment 1208,via an communication link that includes HDMI optical communicationsystem 100.

System architecture 1200 demonstrates how a plurality of different HDMIsources can be connected to an HDMI sink via HDMI optical communicationsystem 100 using optical communication links, with HDMI opticalcommunication system 100 being used to implement each opticalcommunication link. In one aspect, HDMI optical communication system 100may be implemented as a first active HDMI cable and used to connectdisplay device 1204 with the video source 1202. HDMI opticalcommunication system 100 may be implemented as a second active HDMIcable and used to connect display device 1204 with the audio equipment1208 (e.g. an audio output device), supporting the audio return function(ARC). Other control devices 1206 may also connected to display device1204 via HDMI optical communication system 100 may be implemented as athird HDMI cable of a traveling source. Tests show that the low-speedforwarding circuit (i.e., HDMI optical communication system 100) cansupport the video source equipment to transmit video signals of HDMI1.4,HDMI2.0 and HDMI2.1 protocols, and can support arbitrary switching ofresolution from 480p to 4K/60 Hz, CEC control function and audio returnfunction.

Although the present disclosure is described in terms of certain exampleembodiments, other embodiments will be apparent to those of ordinaryskill in the art, given the benefit of this disclosure, includingembodiments that do not provide all of the benefits and features setforth herein, which are also within the scope of this disclosure. It isto be understood that other embodiments may be utilized, withoutdeparting from the scope of the present disclosure.

What is claimed is:
 1. A decoding and forwarding unit comprising: an SDAinterface configured to transmit or receive one or more SDA signalsassociated with an HDMI communication protocol; an SCL interfaceconfigured to transmit or receive one or more SCL signals associatedwith the HDMI communication protocol; a slave state machine configuredto identify and resolve half-duplex communication resource contentionbetween one or more transmitted SDA and SCL signals, and one or morereceived SDA and SCL signals; and an input/output direction controlconfigured to switch a direction of communication of the SDA interfaceand the SCL interface respectively, to transition between associatedreceive and transmit modes, based on the resolving.
 2. The decoding andforwarding unit of claim 1, further comprising a reconfigurable ringoscillator to provide a clock input to the slave state machine.
 3. Thedecoding and forwarding unit of claim 2, wherein the ring oscillator isconfigurable to operate in a frequency range of 100 MHz to 400 MHz. 4.The decoding and forwarding unit of claim 1, wherein the slave statemachine performs filtering and reshaping operations on the SDA and SCLsignals.
 5. The decoding and forwarding unit of claim 1, wherein thedecoding and forwarding unit is included in an HDMI source terminal. 6.The decoding and forwarding unit of claim 1, wherein the decoding andforwarding unit is included in an HDMI sink terminal.
 7. The decodingand forwarding unit of claim 1, further comprising a read requestcontrol configured to support one or more read requests associated withthe HDMI communication protocol.
 8. The decoding and forwarding unit ofclaim 1, further comprising a clock extension control configured tosupport one or more clock stretching functions associated with the HDMIcommunication protocol.
 9. The decoding and forwarding unit of claim 1,wherein the slave state machine governs processing of any combination ofone or more read request functions and clock stretching functionsassociated with the HDMI protocol.
 10. The decoding and forwarding unitof claim 1, wherein the SDA signals and the SCL signals aretime-division demultiplexed signals.
 11. A CEC decoding and forwardingunit comprising: a CEC analyzer configured to receive a first CEC signaland a second CEC signal, wherein each of the first CEC signal and thesecond CEC signal is a CEC signal associated with an HDMI communicationprotocol; a CEC arbitrator configured to: analyze the first CEC signaland the second CEC signal; and resolve half-duplex communicationresource contention between the first CEC signal and the second CECsignal; and an input/output direction control configured to prioritize atransmission of the first CEC signal over a transmission of the secondCEC signal.
 12. The CEC decoding and forwarding unit of claim 11,wherein a CEC transaction direction associated with the transmission ofeither the first CEC signal or the second CEC signal is held unchangedtill the CEC transaction is completed.
 13. The CEC decoding andforwarding unit of claim 11, further comprising a CEC transmit andreshape unit configured to reshape either the first CEC signal or thesecond CEC signal, wherein the reshaping is performed only when thefirst CEC signal or the second CEC signal is being transmitted,respectively.
 14. The CEC decoding and forwarding unit of claim 11,further comprising a local oscillator configured to supply a clocksignal to at least one of the CEC analyzer, the CEC arbitrator, theinput/output direction control, and the CEC transmit and reshape unit.15. The CEC decoding and forwarding unit of claim 11, further comprisinga plurality of CEC analyzers interconnected as a plurality of nodes in aCEC connection topology, wherein the CEC connection topology isconfigured to relay one or more CEC requests generated by one or more ofthe nodes, while preventing one or more CEC request deadlocks over theCEC connection topology.
 16. The CEC decoding and forwarding unit ofclaim 15, wherein the deadlocks are prevented by each node performing alocal CEC arbitration with each adjacent node.
 17. The CEC decoding andforwarding unit of claim 16, wherein communication from a node thatfails a local CEC arbitration is blocked from being transmitted.
 18. TheCEC decoding and forwarding unit of claim 15, wherein the CEC connectiontopology corresponds to an HDMI-based network.
 19. The CEC decoding andforwarding unit of claim 15, wherein each node communicates with anadjacent node using a point-to-point communication protocol.
 20. An HDMIsignal encoding scheme for generating an HDMI data packet, thegenerating comprising: assembling a sequence of HDMI signals, thesequence of HDMI signals comprising ARC, SDA, ARC, SCL, ARC, CEC, ARC,and HPD signals; encoding one or more digital HDMI signals in thesequence of HDMI signals using Manchester encoding; and designating astart of the HDMI data packet by using an elongated last bit sequencefrom a previous HDMI data packet immediately preceding the HDMI datapacket.
 21. The HDMI signal encoding scheme for generating an HDMI datapacket of claim 20, further comprising repeating the sequence of HDMIsignals multiple times to construct the HDMI data packet.
 22. The HDMIsignal encoding scheme for generating an HDMI data packet of claim 20,wherein the ARC signal is an analog signal.
 23. The HDMI signal encodingscheme for generating an HDMI data packet of claim 20, wherein insertingthe ARC signal in every other data slot ensures that the ARC signaloccupies a bandwidth of approximately 50% of the HDMI data packet. 24.The HDMI signal encoding scheme for generating an HDMI data packet ofclaim 20, wherein the elongated last bit sequence is used as a headerfor the HDMI data packet.